The Automation Core

HBM Alternatives Explained: Fractile Stacks DRAM on the Chip, Axelera Bets on LPDDR6

HBM Alternatives Explained: Fractile Stacks DRAM on the Chip, Axelera Bets on LPDDR6

November 13, 2026 · 3D Stacked DRAM, AI Inference, Axelera Titania, Fractile, HBM Alternatives, LPDDR6, The Engineering Core, TSMC CoWoS,
Huawei's Tau Law Explained: "Equivalent 1.4nm" Is a Stacking Trick, Not a Shrink

Huawei's Tau Law Explained: "Equivalent 1.4nm" Is a Stacking Trick, Not a Shrink

November 12, 2026 · 3D IC, Huawei Tau Law, Hybrid Bonding, Kirin 2026, LogicFolding, Semiconductor Scaling, The Engineering Core, TSMC SoIC,
TSMC A16 Explained: The Chip Industry Changed the Ruler, Not the Physics

TSMC A16 Explained: The Chip Industry Changed the Ruler, Not the Physics

November 11, 2026 · Angstrom Node, Gate Pitch, Metal Pitch, Moore's Law, Process Node Naming, Semiconductor Scaling, The Engineering Core, TSMC A16,
NPO vs CPO Explained: It's Not Distance, It's Board Assembly vs Chip Packaging

NPO vs CPO Explained: It's Not Distance, It's Board Assembly vs Chip Packaging

November 10, 2026 · Advanced Packaging, AI Networking, Co-Packaged Optics, Near-Packaged Optics, NPO vs CPO, Optical Interconnect, pJ per bit, Silicon Photonics, Spectrum-X Photonics, The Engineering Core, TSMC COUPE,
CPO Germanium Photodetectors Explained: Silicon Is Blind to Its Own Light, So TSMC Grows a Germanium Eye

CPO Germanium Photodetectors Explained: Silicon Is Blind to Its Own Light, So TSMC Grows a Germanium Eye

November 09, 2026 · 1310 nm, AI Networking, Co-Packaged Optics, COUPE, CPO, Ge-on-Si, Germanium Photodetector, Optical Receiver, Silicon Photonics, SoIC, The Engineering Core, TIA, TSMC,
TSMC 2T0C Explained Like a Blanket on a Furnace: Why Zero Capacitors Still Fear Heat

TSMC 2T0C Explained Like a Blanket on a Furnace: Why Zero Capacitors Still Fear Heat

November 09, 2026 · 1T1C, 2T0C, 3D DRAM, BEOL Memory, IGZO, Memory Wall, On-Die Cache, Oxide Semiconductor, Semiconductor Process, SRAM, The Engineering Core, TSMC,
TSMC N2 Nanosheets Explained: How Billions of Floating Silicon Bridges Don't Collapse

TSMC N2 Nanosheets Explained: How Billions of Floating Silicon Bridges Don't Collapse

November 07, 2026 · 2nm, ALD, Channel Release, FinFET, GAA, Gate-All-Around, Inner Spacer, N2, Nanosheet, Selective Etch, Semiconductor Process, The Engineering Core, TSMC,
CPO Silicon Photonics Explained: Why Si Can't Emit Light, So InP Lasers Stay External

CPO Silicon Photonics Explained: Why Si Can't Emit Light, So InP Lasers Stay External

November 06, 2026 · AI Datacenter, Broadcom, COUPE, CPO, ELS, External Laser Source, Indirect Bandgap, InP Laser, Modulator, NVIDIA, Silicon Photonics, The Engineering Core, TSMC,
TSMC CoWoP Explained: What You Gain (and Lose) Dropping the ABF Substrate

TSMC CoWoP Explained: What You Gain (and Lose) Dropping the ABF Substrate

November 05, 2026 · ABF Substrate, Advanced Packaging, AI Chip, CoWoP, CoWoS, HBM, NVIDIA Rubin, PCB Packaging, Silicon Interposer, The Engineering Core, TSMC,
CoWoS Warpage Explained: Why NVIDIA Blackwell Needs Liquid Cooling (It's the Temperature Swing, Not the Heat)

CoWoS Warpage Explained: Why NVIDIA Blackwell Needs Liquid Cooling (It's the Temperature Swing, Not the Heat)

November 04, 2026 · Advanced Packaging, B200, CoWoS, CoWoS-L, CTE Mismatch, Liquid Cooling, NVIDIA Blackwell, The Engineering Core, Thermal Cycling, TSMC, Warpage,
Older articles →

© The Automation Core. All rights reserved.