Huawei's Tau Law Explained: "Equivalent 1.4nm" Is a Stacking Trick, Not a Shrink

Bottom line: Huawei's "Tau Law" isn't a process breakthrough. It's an architectural workaround. Its core technique, LogicFolding, splits a planar circuit into two tiers and hybrid-bonds them on top of each other. Density really does go up, but because the footprint shrinks, not the transistors. Here are the numbers, and where TSMC already stands on the same road.

This piece expands a post from our Facebook page: Did Huawei's Tau Law just beat TSMC's process limits?

What happened

• On May 25, 2026, Huawei semiconductor chief He Tingbo presented the Tau Law at IEEE ISCAS 2026 in Shanghai: replace "geometric scaling" with "time scaling," targeting 1.4nm-equivalent density by 2031.
• Tau is the circuit time constant, the RC delay. LogicFolding spreads critical-path logic across two stacked tiers, so wires get shorter, parasitic R and C drop, and signals arrive sooner.
• Huawei's Kirin 2026 claims: density from 155 to 238 MTr/mm² (about +54%), roughly 41% better performance-core efficiency, about 13% higher peak clock, all on the same process node.
• The July V2 paper added detail: wafer-to-wafer hybrid bonding at a 1.5 µm pitch, with targets of 292 MTr/mm² in 2030 and 400 in 2031.
• Related: why "equivalent X nm" claims deserve suspicion, in yesterday's TSMC A16 Explained.

Keep these apart:
Geometric scaling (TSMC N2, A16) = make the transistor itself smaller.
LogicFolding (Huawei) = same transistors, circuit folded into two tiers.
You can do both. Doing only the second gives you a lower ceiling.

Engineering point 1: stacked density, so only 1.54x

Two tiers should halve the footprint and double density. The actual jump, 155 to 238, is 1.54x, because both tiers give up area to vertical connections and routing. That mirrors TSMC's CFET research, which stacks nMOS on pMOS: industry estimates put the area gain at 1.5 to 2x, never a clean 2x. TSMC showed CFET transistors at a 48 nm gate pitch at IEDM 2023 and a working CFET inverter in 2024. Going vertical is not a Huawei invention.

Engineering point 2: bond density is the key, and Huawei's is decent

Huawei's paper defines a "gear ratio": bond pitch divided by top-metal pitch. The closer it gets to 1, the more the two wafers behave like two metal layers of one chip, and the better folding works. Our math: a 1.5 µm pitch is about 444,000 connections per mm². TSMC's chip-on-wafer SoIC moved from 9 µm to 6 µm in volume (about 28,000 per mm²) and targets 4.5 µm by 2029. To be fair, wafer-to-wafer bonding is inherently easier to make fine than chip-on-wafer (TSMC offers SoIC-X wafer-on-wafer too), so this is not a straight scoreboard.

Engineering point 3: wafer-to-wafer means compound yield

With wafer-to-wafer bonding you can't pick known-good dies first. A bad top die kills a good bottom die. Our math: two tiers at 80% yield each give about 64% after stacking; at 60% each you're down to 36%. Huawei is building on a restricted 7nm-class process, and the lower the base yield, the more that squaring hurts. Every extra tier also adds another round of lithography, deposition and CMP, nearly doubling tool time and materials.

Engineering point 4: it didn't melt because speed was traded for voltage

Our original post worried that heat gets trapped between stacked layers. Huawei's answer: at matched performance, voltage drops from 1.1 V to 0.9 V, power falls 41%, and power density falls 5.6%. In other words, it spent the time saved by folding on lower voltage, not on raw clock speed. That makes sense for a phone, but hot spots at full boost still need real-device testing. TSMC's path combines N2P, A16 backside power and SoIC, so it gets shrink plus stack.

Open questions

• 238 MTr/mm², +41% efficiency and −5.6% power density are Huawei's own figures, with no independent teardown yet.
• "1.4nm-equivalent" is a density conversion, not a process node. An Omdia analyst told The Register it is packaging-driven density and not comparable to a real TSMC or Intel 1.4nm transistor.
• The 444,000 and 28,000 connection counts and the 64%/36% yields are our arithmetic to show scale, not product measurements.
• Huawei's own paper lists EDA as the top unsolved challenge: tools must treat two bonded wafers as one chip at the cell level.

Related videos

Beyond CoWoS: Why TSMC's SoIC is the Real Future of Chips

You Think TSMC's CoWoS is Just One Technology? Think Again! (S, R, & L Explained)

Is LogicFolding a genuinely new path, or a smart compromise forced by export controls? And how big would the gap get if TSMC folded N2 into two tiers? Tell us in the comments.

Sources: Huawei newsroom, Tau Law announcement (May 25, 2026); Tencent News on the V2 paper (July 2026); EE Times Asia; The Register (Omdia comment); TrendForce; Tom's Hardware, "The current state of Hybrid Bonding in 2026"; TSMC Research CFET papers (IEDM 2023/2024); original Facebook post. Figures marked as our math are not official.
Videos by @TheEngineeringCore-v. Published on The Automation Core.
Original post: https://www.facebook.com/1147074221177116/posts/1158720626679142
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