HBM Alternatives Explained: Fractile Stacks DRAM on the Chip, Axelera Bets on LPDDR6

Bottom line: AI inference is increasingly limited not by compute but by how fast memory can feed the chip. The standard answer is HBM on TSMC CoWoS, and both are sold out. This week two startups offered opposite workarounds: Fractile stacks DRAM on top, Axelera swaps HBM for LPDDR6. Here is what each one is really betting on, with numbers.

This piece expands a post from our Facebook page: Fractile raised $720M to route around HBM (and our take on Axelera: Axelera Titania and LPDDR6).

What happened

• On Nov 11, UK startup Fractile closed a $720M Series C at about a $7B post-money valuation, co-led by Thrive, Founders Fund, Lightspeed and Redpoint, with Alphabet's CapitalG and the UK Sovereign AI Fund joining. Total raised: about $955M.
• Fractile's design drops HBM and packages standard DRAM directly on top of its logic, claiming far more bandwidth than HBM and far more capacity than SRAM. First chips and systems are due in 2027.
• Bloomberg reported in August that Anthropic tentatively agreed to buy about $250M of Fractile chips. Neither company confirmed it.
• On Nov 12, Dutch company Axelera AI detailed Titania: two chiplets per package, 2.5 PFLOPS FP8 at 400 W, 128 GB of LPDDR6 at 2,458 GB/s. Production starts Q3 2027, with over $300M in customer commitments.

Keep these apart:
HBM + CoWoS = memory sits next to the chip, wired side by side through an interposer.
Fractile = memory sits on top of the chip, wired vertically, shortest possible path.
Axelera = memory stays beside the chip, but it's cheap, high-capacity LPDDR6, and the architecture squeezes every bit of bandwidth.

Engineering point 1: why inference is a bandwidth problem

When an LLM generates text, every token requires reading the active weights from memory. So the single-user speed ceiling is roughly memory bandwidth ÷ bytes read per token. Our math: take a MoE model with 671B total and about 37B active parameters (DeepSeek-V3 class). At FP4, each token reads about 18.5 GB. One Titania package at 2,458 GB/s tops out near 130 tokens/s; a full AX8 server at 19.6 TB/s near 1,060. Real numbers will be lower once interconnect, KV cache and utilization bite, but the rule holds: bandwidth sets speed, capacity decides whether the model fits.

Engineering point 2: Fractile bets on distance, SoIC-style

On CoWoS, HBM sits beside the GPU and data travels millimeters across the interposer. Fractile puts DRAM directly over the compute cores, cutting the path to microns and letting connections cover the whole die area instead of just the edge. It's the same family as AMD 3D V-Cache, where TSMC SoIC hybrid bonding stacks SRAM on a CPU, except the stacked layer is far denser DRAM. Hybrid bonding, which we covered in Huawei's Tau Law, becomes a memory fix here. Fractile hasn't disclosed bandwidth figures or its foundry, so those wait for 2027 silicon.

Engineering point 3: Axelera bets on capacity and skips the packaging queue

LPDDR6 offers less bandwidth per device than HBM, but it's a commodity part for phones, AI PCs and cars, in standard packaging, so no TSV stacking and no CoWoS slot. Micron has said HBM3E uses roughly three times the wafer supply of DDR5 for the same bits, so the same wafer yields a lot more capacity as standard DRAM. Axelera's bet is that MoE models are huge in total but small per token. Our math: 1.6T parameters at FP4 is about 800 GB, which fits in AX8's 1 TB with room for KV cache, at 5-6 kW air-cooled. Two fit in a legacy 15 kW rack.

Engineering point 4: the real hurdles are heat, yield and supply

First, DRAM hates heat: JEDEC doubles the refresh rate above 85°C and leakage climbs. Fractile parks DRAM on top of the hottest die in the system, so thermal design is make-or-break. Second, yield compounds: one bad layer scraps the stack, so known-good-die testing matters. Third, supply: LPDDR6 still comes from Samsung, SK hynix and Micron, just with multi-sourcing leverage. Our original post floated Taiwanese specialty DRAM makers like PSMC or Winbond as Fractile partners; that is industry speculation, not confirmed. And TSMC? If HBM wins, CoWoS gets tighter. If 3D stacking wins, SoIC-class bonding gets busier. It's at the table either way.

Open questions

• Fractile's "up to 100x faster, 90% less energy" and Axelera's "7x throughput per watt, 20x TCO" are company claims; Axelera labels its figures as simulations. Neither has production silicon measured.
• Fractile hasn't disclosed per-chip bandwidth, capacity, process node or foundry.
• The 130 and 1,060 tokens/s and 800 GB figures are our theoretical upper bounds from published specs, not measurements.
• Any PSMC or Winbond partnership is speculation with no official announcement.

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Which bet proves itself first in 2027: Fractile stacking up, Axelera swapping out, or does HBM on CoWoS simply stay king? Tell us in the comments.

Sources: TechCrunch, SiliconANGLE, SiliconReport (citing Reuters, Bloomberg, FT), Balderton and Lightspeed investment notes (Nov 11, 2026); Axelera AI press release and Titania product page (Nov 12, 2026); original Facebook post. Figures marked as our math are not official.
Video channel: @TheEngineeringCore-v. Published on The Automation Core.
Original post: https://www.facebook.com/1147074221177116/posts/1159830179901520
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