TSMC N2 Nanosheets Explained: How Billions of Floating Silicon Bridges Don't Collapse

Bottom line: TSMC N2 is the company's first nanosheet gate-all-around (GAA) node, and in cross-section its channels look like they're hovering in mid-air. That's not a trick of the microscope so much as a chain of chemistry: grow a Si/SiGe layer cake, remove the SiGe with near-perfect selectivity, then deposit the gate into gaps only a few nanometers wide. The step that can wreck everything is the release itself. Let any liquid in there and surface tension will glue the sheets together.

This piece expands a post from our Facebook page: How do TSMC N2 nanosheets “float”?

What happened

• TSMC started N2 volume production in Q4 2025. Versus N3E, it quotes 10–15% more speed at the same power, or 25–30% less power at the same speed, with roughly 1.15x logic density.
• Why FinFET ran out of road: a fin gives the gate three sides. Below the 3 nm class, leakage under the fin and short-channel effects get hard to control. Nanosheets lay the channel flat, stack several, and let the gate surround each one.
• N2 also adds NanoFlex, which lets designers mix standard cells of different heights on one die, trading speed against area. That flexibility comes from being able to tune sheet width.
• TSMC hasn't published N2's sheet count or thickness. Public demos such as IBM's 2021 2 nm chip used three stacked sheets a few nanometers thick, so treat that as the order of magnitude.

The cross-section illusion: slice across the current flow and a 2D image shows no supports. Look along the current and each sheet is welded to the source/drain epitaxy at both ends, like a suspension bridge with towers at either side and a free span for the gate to wrap.

Engineering point 1: the layer cake

It starts with alternating epitaxial layers of pure Si (the future channels) and SiGe (temporary scaffolding), patterned together into fin-like stacks. The two lattices match closely enough to grow cleanly, but they etch very differently, and every later step depends on attacking SiGe while leaving Si alone. Ge fraction, layer thickness and thermal budget all shift that balance; published work shows hotter anneals smear Ge outward and slow the SiGe etch.

Engineering point 2: inner spacers, a firewall before demolition

Before source/drain epitaxy, the SiGe is recessed sideways by a few nanometers and the cavities are filled with a nitride-type dielectric: the inner spacer. Electrically, it separates the future metal gate from source/drain, cutting parasitic capacitance and shorts. Mechanically, it's the bearing pad the sheets hang from. One simulation study found that thinning the inner spacer from 3 nm to 1 nm increased mid-sheet deflection by about 1.8x. Recess depth has to match across every layer, and gas-phase etching has been reported to keep that variation under 1 nm.

Engineering point 3: why the release has to be dry

Channel release removes all the SiGe so the Si sheets hang free. With a wet etch, liquid left between sheets during drying pulls them together, a failure called stiction. Our rough estimate (not official): Laplace pressure ΔP ≈ 2γ/g. With water at γ ≈ 0.072 N/m and a gap of about 10 nm, ΔP comes to roughly 14 MPa, around 140 atmospheres, acting on silicon only a few nanometers thick. Hence the move to non-plasma, gas-phase etches. Research groups report SiGe:Si selectivity of about 56–87, and IBM showed 150:1 against SiGe25% at IEDM 2019, with Si loss per side held under 1 nm.

Engineering point 4: ALD, filling the gaps atom by atom

Once the scaffolding is gone, only a few nanometers separate the sheets. An interfacial oxide, a high-k dielectric and work-function metals now have to coat every surface of every sheet, with thickness control measured in ångströms. Only atomic layer deposition does that. If the bottom sheet ends up with a thinner stack than the top one, threshold voltages drift apart, which is one reason GAA yields are harder to ramp than FinFET. Our page summed it up in four moves: stack, wall off, demolish, pour. Original post.

Open questions

• TSMC doesn't disclose N2 sheet count, thickness or release chemistry; the flow above is the generic GAA process from public literature.
• The 14 MPa figure assumes perfect wetting and a 10 nm gap. It's an order-of-magnitude estimate, not a measurement.
• Selectivity numbers come from separate research groups, not TSMC production data.
• N2 yield and cost figures circulating publicly are mostly supply-chain rumor.

Related videos

Beyond CoWoS: Why TSMC's SoIC is the Real Future of Chips

You Think TSMC's CoWoS is Just One Technology? Think Again! (S, R, & L Explained)

Which step do you think limits GAA yield most: the release etch, the ALD fill, or will CFET make both look easy? Tell us in the comments.

Sources: TSMC N2 public specs and production announcement; IEDM 2019 dry selective SiGe etch paper; MDPI Nanomaterials 2026 studies on inner-spacer and channel-release gas etching; MDPI Electronics 2021 nanosheet mechanical-stability simulation; original Facebook post. Figures marked as our estimate are not official.
Videos by @TheEngineeringCore-v. Published on The Automation Core.
Original post: https://www.facebook.com/1147074221177116/posts/1150392860845252
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