TSMC 2T0C Explained Like a Blanket on a Furnace: Why Zero Capacitors Still Fear Heat

Bottom line: Before you buy the "TSMC builds 3D DRAM" headline, split two cells: 1T1C versus 2T0C. One is running out of capacitor height; the other deletes the capacitor with oxide semiconductors—and inherits heat. Publicly, TSMC still brands itself a dedicated logic foundry, and the silicon it has shown is a BEOL oxide 1T1C test chip from VLSI 2025, not a shipping 2T0C product.

This expands our Facebook post: Is TSMC really building 3D DRAM? 1T1C vs 2T0C

What happened

• Reports said TSMC was exploring advanced memory / 3D DRAM for AI customers. TSMC's reply: core business is dedicated IC foundry.
• At VLSI 2025 it showed a BEOL oxide 1T1C test chip—about 0.75 V, retention >128 ms, R/W <8 ns, endurance >10¹⁴—pitched as denser on-die memory than SRAM.
• Academia is pushing IGZO 2T0C: a 2025 Science Advances 8×8 stacked array held bits beyond 100 s.
• Our page's line: 1T1C isn't broken so much as out of vertical room; 2T0C trades capacitor pain for thermal pain.

Metaphors: a 1T1C capacitor is Taipei 101 on a fingernail (aspect ratio >50:1). 2T0C knocks the water tower down and uses two oxide transistors' gate parasitics as a tiny, almost leak-free bucket.

Engineering point 1: why 1T1C hits a wall

1T1C stores charge in a capacitor. Shrink the footprint and the capacitor grows taller—often past 50:1—or must lie on its side in nanometer trenches. Silicon leaks, so the array refreshes every few tens of milliseconds, and a read destroys the bit. Under AI load, that refresh tax eats bandwidth and watts.

Engineering point 2: why 2T0C looks AI-native

2T0C drops the capacitor. Oxide channels such as IGZO (band gap roughly >3 eV) park charge on gate parasitics: ultra-low off current, retention into tens or hundreds of seconds, process temperatures around 300–400°C that fit above a logic die's BEOL metal. For a foundry that looks like "add transistors in the interconnect," not "sell DDR sticks."

Engineering point 3: heat — a blanket on a furnace

Oxides conduct heat on the order of 1% of silicon. Stack tiers on a multi-hundred-watt GPU and you have thrown a blanket over a furnace. Past roughly 85°C (a discussion warning band, not a datasheet), leakage rises and the retention story collapses. Low mobility also keeps 2T0C out of L1/L2; it fits a fat last-level on-die cache better.

Engineering point 4: rumor, paper, product

Three buckets: ① TSMC's public line on commodity 3D DRAM is still pure-play foundry; ② what it has shown is BEOL oxide 1T1C—capacitor included; ③ 2T0C / IGZO stacks live mostly in papers and roadmaps, where memory vendors have been filing for years. PBTS-driven Vth drift and patents remain gates. Original post.

Open questions

• Customer 2T0C or branded 3D DRAM volume: unconfirmed; treat press as leads.
• Full capacitor stack, oxide recipe and host node for the VLSI 2025 chip: not fully public.
• ~85°C and "~1% of silicon" thermal conductivity are order-of-magnitude / discussion figures, not TSMC product specs.

Related videos

The REAL Reason RAM Prices Are Exploding (It's Not Inflation)

Beyond CoWoS: Why TSMC's SoIC is the Real Future of Chips

Will on-die memory win as capacitor-free 2T0C, or as BEOL 1T1C that keeps the capacitor upstairs? Comment below.

Sources: TSMC foundry-focus media statements; public reports of the 2025 VLSI BEOL oxide 1T1C test chip (0.75 V, >128 ms, <8 ns, >10¹⁴); Science Advances 2025 IGZO 2T0C array; industry 1T1C aspect-ratio / refresh background; original Facebook post.
Videos by @TheEngineeringCore-v. Published on The Automation Core.
Original post: https://www.facebook.com/1147074221177116/posts/1154136300470908
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