CPO Silicon Photonics Explained: Why Si Can't Emit Light, So InP Lasers Stay External

Bottom line: Silicon builds nanometer transistors — and still cannot emit light efficiently. It is an indirect-bandgap semiconductor: recombination mostly makes heat, not photons. That is materials physics, not a TSMC process limit. Gen-1 CPO (Broadcom / TSMC COUPE path) therefore puts the "lamp outside": front-panel replaceable CW InP ELS, fiber into the PIC, on-chip modulators for 0/1. Bonding III–V onto silicon is the ideal; CTE, heat and aging still block volume.

Source post: FB — why silicon won't lase, so CPO keeps lasers external

What happened

• Physics floor: Si = indirect bandgap → inefficient radiative recombination. Silicon photonics still guides and modulates near-IR light in ~220 nm SOI waveguides; detectors often use Ge-on-Si; laser gain media need III–V (typically InP).
• Gen-1 CPO architecture: continuous-wave (CW) external laser modules (often InP) on a front-panel / replaceable ELS; light fibered into the PIC; on-chip modulators (microring / MZM / EAM) imprint data. Lasers stay away from hot switch ASICs; failed lasers can be swapped without scrapping the whole CPO module.
• TSMC COUPE / CPO public narrative: CPO volume production around 2H2026; silicon photonics share of the optical-transceiver market >50% by 2027 (VP Hsu quotes via Taipei Times / SEMICON Taiwan coverage). Named bottlenecks: lasers, fiber, connectors, photodetectors, packaging, optical coupling, test.
• NVIDIA Spectrum-X / Quantum-X CPO reporting (2026): external CW InP; Quantum-X800-style designs described as many SiPh engines sharing fewer high-power CW lasers (one report ~4 engines : 1 laser) vs pluggable EML-per-lane — laser count down, high-power CW InP demand up. Lumentum has discussed CW supply gaps / premiums in earnings commentary.
• Roadmap: TSMC slides (TechOrange / TechNews) mention later CPO-OI integrating modulators / amplifiers / lasers on the COUPE backside — no production date. III–V bonding onto Si remains the ideal; CTE, heat and reliability block volume today.

One-line contrast: Mainstream = "lamp outside" (ELS + fiber + on-chip modulators). Ideal = "bond the emitter onto silicon" (III–V heterogeneous integration). The first ships in Gen-1 CPO; the second is research-hot and volume-cold.

Point 1: Indirect bandgap is not a process miss

Direct-bandgap materials (InP, GaAs) recombine at matching crystal momentum and emit a photon. Silicon's band extrema sit at different k-points, so recombination needs phonon help and is inefficient — current becomes heat. Silicon is therefore an excellent waveguide and modulator platform (~220 nm SOI) and a poor intrinsic laser gain medium. Calling external CPO lasers a foundry or Broadcom process compromise misreads a materials limit as an engineering shortcut.

Point 2: External ELS trades coupling loss for serviceability and thermal isolation

Front-panel replaceable CW InP ELS costs fiber coupling loss and alignment tolerance. Payoff: lasers stay off the switch ASIC's hot zone, and a failed laser swaps without scrapping the CPO. Author qualitative note: if the ASIC package surface is ~85–100°C while InP prefers a cooler junction, millimeter-scale co-packaging worsens threshold and aging — a thermal motivation, not a measured ΔT. The PLC fan page's "lamp outside" framing points the same way.

Point 3: Fewer lasers ≠ less InP demand

Pluggables often use one EML per lane. Shared-CW CPO feeds many SiPh engines from fewer high-power CW InP sources. Author illustration: one CW laser for four engines → count −75%, but ~4× optical power before the split (not a datasheet). So the industry can say both "laser count fell" and "high-power CW InP is tight / premium-priced" (Lumentum and peers in earnings commentary).

Point 4: Heterogeneous integration is the ideal; CTE and reliability are the invoice

Bonding InP gain onto silicon shortens the path and cuts coupling hardware — slides love it. In practice III–V/Si CTE mismatch drives strain and cracks; add junction heat and aging, and volume yield plus field life stay hard walls. TSMC CPO-OI optical-interposer mentions (modulators / amplifiers / lasers on the COUPE backside) still carry no production date. Until then, Gen-1 external ELS is the shippable path. Fan-page contrast: FB source post.

Open questions

• CPO 2H2026 volume and SiPh >50% transceiver share by 2027 are public narrative / press quotes, not audited shipment figures in this article.
• "~4 engines : 1 laser" is a reported architecture description — do not treat it as a fixed ratio across all CPO products.
• CPO-OI laser-integration slides have no production date; heterogeneous bonding volume timing remains outlook, not a schedule.
• Author thermal motivation and 4× power illustration are qualitative / order-of-magnitude, not lab measurements or vendor datasheets.

Related videos

Silicon Photonics: How Light Moves Into the Switch

You Think TSMC's CoWoS is Just One Technology? (S, R, & L Explained)

How many CPO generations can "lamp outside" carry before III–V heterogeneous integration breaks through? Tell me in the comments.

Sources: indirect-bandgap / silicon-photonics fundamentals; TSMC COUPE / CPO public narrative and Taipei Times / SEMICON Taiwan quotes of VP Hsu; NVIDIA Spectrum-X / Quantum-X CPO industry reporting; Lumentum and peers on CW laser supply in earnings commentary; TechOrange / TechNews recaps of TSMC CPO-OI roadmap slides; PLC fan-page source post. Figures marked "author estimate," "reported" or "public narrative" are not audited shipment numbers.
Published on The Automation Core. Videos by @TheEngineeringCore-v. This topic is hot on the fan page — join the discussion: PLC Facebook page.