Renesas 650V GaN Dual-Side Cooling in 8×8 mm: Packing More Power into 800V→48V AI IBCs

 

Bottom line: On 30 September 2026, Renesas Electronics announced what it positions as the industry's first 650V GaN FET with dual-side cooling (DSC): TP65H020G4PLSGBD, built on Gen IV Plus D-Mode technology, with 20 mΩ on-resistance (company: among the lowest in the 650V class) in an ultra-compact 8×8 mm PQFN. The device targets megawatt-scale AI data centers moving to 800 V HVDC architectures — specifically the intermediate bus converter (IBC) that steps 800 V down to 48 V, 12 V, or 6 V, plus battery-backup (BBU) and capacitor-bank (CBU) stages in sidecar power racks. It supports operation up to about 700 V. Renesas is sampling major AI data-center OEMs/ODMs now, with mass production planned for mid-2027. Read this as a rack/sidecar GaN packaging and thermal-path story — not the pending Infineon × Eaton MVSST medium-voltage SST SiC-supply piece, not Toshiba IX800's industrial 3.3 kV module, and not onsemi EPP wafer-as-package.

What happened

• Device: TP65H020G4PLSGBD; 650V GaN; Gen IV Plus; D-Mode; R_DS(on) = 20 mΩ (company claim).
• Package: dual-side-cooled 8×8 mm PQFN; ~57% smaller footprint than a 10×15 mm TOLT; ~10% lower top-side thermal impedance via two-sided heat paths.
• Use cases: 800V HVDC AI halls; IBC (800→48/12/6 V), BBU, CBU; sidecar power racks.
• Drive model: high gate threshold, built-in freewheeling diode, low Q_g/C_oss; driveable with a standard silicon gate driver — no negative gate bias, no dedicated E-mode driver required (company narrative).
• Reference design: 6 kW 800V-to-48V LLC DCX with RA6T3 MCU — 2.6 kW/in³ density; full-load efficiency ~0.21% higher than an equivalent TOLT board (company per-module test).
• Cadence: sampling now; mass production mid-2027; demo at OCP Global Summit, San Jose, 12–15 October 2026.

How this differs from Infineon × Eaton MVSST: MVSST is about medium-voltage grid in → facility 800 VDC out via a solid-state transformer platform and SiC device supply. Today's Renesas story is what happens after 800 V is already inside the hall — how the rack/sidecar IBC and backup stages pack more conversion into less board and thermal budget with GaN. Same 800V highway; different mile markers.

Four engineering takeaways

1. Dual-side cooling buys thermal headroom before ampere headroom
As rack power climbs from ~120 kW toward megawatt class, designers often run out of board area and heat sink budget before they hit a pure current limit. DSC rejects heat from top and bottom (~10% lower top-side thermal impedance); the 8×8 mm outline is ~57% smaller than TOLT — more FETs or a smaller board for the same cooling envelope.

2. 20 mΩ at 650V is an IBC conduction story
800V→48/12/6 V stages run high current density and often push switching toward MHz to shrink magnetics and capacitors. Low R_DS(on) plus low gate charge and output capacitance attack both conduction and switching loss; Renesas explicitly pitches MHz operation to cut passives and BOM.

3. “Drive it like silicon” lowers the upgrade friction
High V_th, no negative bias, standard silicon gate drivers — the message is that ODMs/OEMs need not rebuild the gate-drive ecosystem to adopt this GaN. Paired with Renesas AUX controllers, drivers, and MCUs, the PR frames a single-source 800V path — a procurement story, not only a die announcement.

4. Reference-design deltas need their test frame
6 kW LLC DCX, 2.6 kW/in³, and +0.21% full-load efficiency vs TOLT are company reference-design / per-module results. They show the package thesis can land on a lab board; they do not guarantee identical numbers on every production sidecar rack. Thermal interfaces, airflow, paralleling, and EMI remain system problems.

Open questions

• When does the full public datasheet (SOA, dynamic R_DS(on), parasitics, reliability conditions) land?
• What baseline defines “industry's first 650V GaN DSC,” and can third parties cross-check?
• Which OEMs/ODMs are sampling, and who is first for volume?
• Full efficiency curves and thermal test conditions for the 800→12V / 6V IBC boards?
• Where does GaN vs SiC cost/loss crossover sit at the same 800V IBC stage?

Watch on The Engineering Core

• From 400V to 800V: The Silicon Carbide Revolution — primary; voltage-architecture and wide-bandgap logic.
• Efficiency vs. Power Factor: The Real Reason AI Data Centers Need SSTs — secondary; why halls want 800 VDC in the first place.

Question for you: As AI halls push 800V buses down to 48/12/6 V, do you expect the next bottleneck to hit GaN package and thermal paths first — or controller/driver ecosystems and copyable reference designs?

Sources: Renesas official press release (2026-09-30, Tokyo) — TP65H020G4PLSGBD / Gen IV Plus / DSC 8×8 mm PQFN. R_DS(on), footprint, thermal impedance, and reference-design density/efficiency deltas are company-published / per-module results, not independent lab measurements by this channel.
Quote: John Wiggenhorn (Senior Product Line Director, High-Voltage GaN, Renesas).
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