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TSMC SPR vs Delta VPD Comparison: Die-Level vs Board-Level Backside Power at 1000 A

· A16, AI server power, backside power delivery, Delta VPD, HBM, I2R loss, IR drop, The Engineering Core, TSMC SPR, vertical power delivery, VRM placement,

Die-level vs board-level backside power

Bottom line: "Backside power" now shows up in two very different headlines: TSMC's A16 process and Delta Electronics' server power modules. They solve different segments of the same problem — getting 1000+ amps into a sub-1V AI accelerator without burning it as I²R heat. This piece expands on a recent post comparing SPR and VPD.

What happened

  • TSMC A16 / Super Power Rail: versus N2P, TSMC cites 8–10% higher speed at the same voltage, 15–20% lower power at the same speed, and up to 1.10x density. The power network moves to the wafer backside and contacts transistor source/drain directly.
  • Delta VPD: shown at NVIDIA GTC and Computex, Delta's vertical VR modules convert 48V to ~0.8V from the back side of the accelerator; Delta says this saves roughly 5–15% of AI accelerator system energy loss. In Aug 2025 Infineon and Delta announced joint VPD modules built on 90 A OptiMOS power stages.
  • Shared idea: shortest vertical path, lowest impedance.

Division of labor: SPR fixes the last micron inside the die; VPD fixes the last ~10 cm on the motherboard. One is a foundry process, the other is power-module and board/package design.

Point 1: I²R at 1000 A

P = I²R. At a few amps 0.1 mΩ is invisible. At 1000 A it is a 100 mV drop — 12.5% of a 0.8 V rail — and 100 W of heat on the PCB. Double the current and loss quadruples; Infineon notes top AI accelerators already exceed 2000 A.

Point 2: Lateral plane resistance

1 oz copper (~35 µm) is about 0.5 mΩ per square. Ten paralleled power/ground planes bring that near 0.05 mΩ/sq. A VRM at the board edge pushing current 10 cm across a 5 cm-wide path sees 2 squares, about 0.1 mΩ — before return path, vias and connectors. Going vertical through a 1–2 mm board with dense via arrays cuts that by an order of magnitude or more. The post's "220 mV to 5 mV, 18 W to 1.2 W (~93%)" are illustrative figures; Delta's published claims are 5–15% system loss savings and TVR efficiency above 94%.

Point 3: Where the VRM went — lateral, vertical, integrated

  • Lateral: regulators ring the socket; easy to cool, long PDN.
  • Vertical: modules under the processor replace the decoupling capacitors there, improving transient response and shrinking passive requirements.
  • Integrated (IVR/on-package): the last regulation stage moves into the package or die (e.g. Intel FIVR), carrying higher voltage closer before stepping down — at the cost of heat and area near the silicon.
  • TSMC SPR goes one layer deeper still: the final hop from metal stack to transistor.

Point 4: How they stack — and what it costs

Model the chain as series resistance: 48V bus → board regulator → board copper → package substrate → on-die metal → transistor. VPD removes board copper; SPR removes front-side on-die metal. No overlap, so the savings add.

  • Real estate: clearing inductors and FETs around the GPU frees room for HBM stacks and high-speed routing; SPR returns front-side metal to signals.
  • Thermal: a 94%-efficient kW-class converter still dumps tens of watts directly behind the GPU, so the board backside needs a cooling plan; SPR's thinned wafer and backside metal reshape on-die hot spots.
  • Serviceability and yield: modules under the GPU are hard to rework; SPR adds bonding and thinning steps.

Open questions

  • A16 volume timing varies by source (2H 2026 to 2027); first customers are supply-chain reports.
  • "~3.5 µm thinning" and the 220 mV/18 W figures have no official TSMC or Delta source.
  • Which GPU platform ships Delta VPD at volume is not disclosed.

Watch next

Where does regulation go next — fully into the package, or higher voltage all the way to the die edge? Join the discussion on our Facebook page.

Sources: TSMC A16 technology page; Delta GTC 2024 and Computex 2024 releases; Infineon–Delta release (Aug 28, 2025); APEC 2025 TVR abstract. Published by The Automation Core · Videos: The Engineering Core YouTube channel

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