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TSMC A16 Backside Power Explained: How Super Power Rail Fights IR Drop vs Intel PowerVia

· AI accelerator, backside power delivery, BSPDN, buried power rail, Intel PowerVia, IR drop, semiconductor process, Super Power Rail, The Engineering Core, TSMC A16, wafer thinning,


Bottom line: For about fifty years, chips have routed power and signals through the same front-side metal stack, the way an old building runs plumbing and wiring through one ceiling duct. Below 2 nm, that duct is so crowded it limits performance. TSMC's A16 answer is blunt: flip the power network to the backside of the wafer and give the front side entirely to signals. Here is the engineering behind it: what IR drop really costs, why the backside wins, how SPR differs from Intel PowerVia and buried power rails, and the new thermal and debug problems that come with a flipped wafer.

What happened

  • Official specs: A16 = nanosheet transistors + Super Power Rail. Versus N2P: +8–10% speed at the same Vdd, −15–20% power at the same speed, up to 1.10x chip density. TSMC's "chip density" is a mixed figure (logic, SRAM and analog); Tom's Hardware lists it as 1.07–1.10x.
  • Schedule: originally slated for 2H 2026 volume production. At the April 2026 North America Technology Symposium, Kevin Zhang said A16 "will be ready for production in 2026," but product ramp depends on customers, so the roadmap now shows 2027. Taiwanese media report it will run in Fab 22 Phase 4 in Kaohsiung.
  • Who uses it: on the Oct 15, 2026 earnings call, asked whether power-grid limits would push more customers to backside power, C.C. Wei said it depends on the product: some AI accelerators may adopt it, phones will not. Supply-chain reports name NVIDIA's Feynman GPU (around 2028) as the first customer; neither company has confirmed it.
  • Competition: Intel shipped backside power first, with PowerVia on 18A in Panther Lake. Samsung plans backside power on SF2Z in 2027.

In one line: front-side power is like bringing electricity in through the roof and running it down a dozen flights of stairs to the machines in the basement. Backside power opens a door right next to the basement. Shorter, fatter paths mean less drop, and the stairwell is freed up for signals.

Point 1: IR drop costs voltage margin, not just watts

IR drop is plain Ohm's law, V = I × R. An AI accelerator runs its core below 1 V but burns on the order of a kilowatt, so the power network carries over a thousand amps. At 1,000 A, every extra 0.05 mΩ in the path costs 50 mV, which is 6–7% of a 0.75 V rail. On the front side, current has to pass down through a dozen-plus metal layers and via stacks, and the bottom layers (M0/M1) are only around a dozen nanometers wide, where copper resistivity climbs further because of surface and grain-boundary scattering. The segments closest to the transistors are the thinnest and the most expensive.

The real cost is the guard-band. Designers must guarantee that the farthest, busiest transistor still sees enough voltage, so the whole die gets a higher supply. Dynamic power scales with voltage squared (P ∝ C·V²·f): a 5% bump in Vdd costs about 10% in dynamic power. A common IR-drop budget is around 10% of VDD; imec used that target in its A14 block-level backside PDN study. Backside power claws that margin back, which is a large part of where "15–20% less power at the same speed" comes from.

Point 2: SPR vs PowerVia vs buried power rail: where the power lands

  • Buried power rail (BPR): imec's early path. The rails sink into the substrate under the cells to free standard-cell height, but they still need feeding from the front side or through nano-TSVs. Think of it as a stepping stone.
  • Intel PowerVia: nano-TSVs from the backside land on the cell's contact level. Simpler and cheaper. On an Intel 4 test chip, Intel reported more than 30% platform voltage-droop improvement, a 6% frequency gain and over 90% standard-cell utilization; for 18A it quotes up to 10x lower worst-case dynamic droop and up to 11% block-area compaction.
  • TSMC SPR: backside contacts connect directly to the transistor's source and drain, so cells need no room for a power via. TSMC says this preserves gate density and device-width flexibility. It is the most complex and expensive variant, which is why TSMC keeps non-SPR N2P and N2X for customers who don't need it.

Put simply, PowerVia delivers power to the cell's front door; SPR delivers it straight into the transistor. A shorter path means lower resistance and more freed front-side routing, which is where most of the 1.07–1.10x density comes from.

Point 3: flip, thin, align: every step is a yield gate

The generic backside flow: build the transistors and the full front-side signal stack → bond the front side to a carrier wafer → flip → grind, CMP and etch the original silicon from hundreds of microns down to a very thin layer → form backside contacts, vias and backside metal (labeled BM0/BM1 in our infographic) → put bumps on the backside for packaging.

Three hard parts. Thinning uniformity has to be controlled at nanometer scale, because over-polishing damages devices. Bonding-induced wafer distortion makes backside lithography harder to align with front-side transistors, and SPR, which lands directly on source/drain, has tighter overlay tolerance than PowerVia. And the extra bonding, thinning and backside metallization steps add cycle time and cost. IDC analysts expect A16's meaningful capacity contribution only after the yield ramp, in 2H 2027 to 2028.

Point 4: the heat path changes and debug tools go blind

In a conventional flip-chip, heat leaves the transistors through thick bulk silicon to the lid. With backside power, the transistors are sandwiched: backside metal and bumps on one side, a dozen-plus mostly dielectric signal layers plus the carrier wafer on the other, and dielectrics conduct heat poorly. Managing hotspots, and whether the carrier and bonding layer need better thermal conductors, is a shared problem for every backside scheme. When Intel unveiled PowerVia, it singled out thermals and debug as the two new challenges that needed dedicated mitigations.

Debug is the other casualty. Failure-analysis staples such as laser voltage probing and photon emission microscopy look at transistors through the backside silicon. Once that side is covered by a power grid, those techniques no longer see through, so test and FA flows have to be rebuilt. On reticle-sized AI accelerators, that directly slows yield learning.

Open questions

  • Claims that front-side power "wastes 10–15% of power" circulate widely, but TSMC has not published such a number. The better-grounded statement is that IR-drop budgets are commonly set around 10% of VDD; actual losses depend on design and workload.
  • 8–10% and 15–20% are TSMC targets versus N2P and are either/or (speed at iso-voltage, or power at iso-speed). No third-party measurement of a shipping A16 product exists yet.
  • NVIDIA Feynman on A16 comes from supply-chain reports, not official confirmation. A16 wafer pricing and yields are not public.

Related videos

Backside power fixes delivery inside one die. Once dies are stacked, power and heat get harder again. Two videos from The Engineering Core YouTube channel pick up from here:

Your turn: backside power makes chips faster and leaner, but the process is costlier and harder to cool. Will it stay an AI-accelerator luxury, or will phone SoCs follow within a few years?

The front-side vs backside infographic that started this post lives on our Facebook page (in Chinese). Feel free to drop a comment there too.

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