The Automation Core

TSMC A16 Backside Power, Explained Simply: Why Flip the Wafer? Super Power Rail in 5 Steps

· AI Chips, backside power delivery explained, BSPDN, carrier wafer bonding, IR drop, semiconductor manufacturing, Super Power Rail, The Engineering Core, TSMC A16, wafer flip, wafer thinning,


Bottom line: A conventional chip is built like a building where every wire, power and data alike, comes in through the ceiling. TSMC's 1.6 nm-class A16 flips the wafer and delivers power from underneath, after grinding the wafer down to a sliver. This post skips the heavy math and walks through it step by step. (The original one-image explainer is on our Facebook page.)

What changed, in one minute

  • Power wiring moves from the front-side metal stack to the wafer backside. TSMC calls it Super Power Rail (SPR).
  • The front side (M1–M10) is handed back entirely to signal routing.
  • TSMC figures vs N2P: 8–10% faster at the same power, or 15–20% lower power at the same speed, and roughly 1.07–1.10x density.

1. The sloppy electrician problem

Picture one ceiling tray holding both the main power feed and the network cables. Fine for a small house. But at 2 nm-class geometries, the wires are smaller than a virus. Thin wires mean higher resistance, so voltage sags on the way to the transistor (IR drop), and the power lines heat up and couple noise into neighbouring signals.

Note: the "10–15% of power wasted" figure in our infographic is an illustrative simplification, not a TSMC number. Designers typically budget IR drop at around 10% of supply voltage; that is a design margin, not measured energy loss.

2. Splitting floor and ceiling

A16 is a renovation: the ceiling (front) carries data only, while floor conduits (backside) carry thick power lines that rise vertically into the transistors. TSMC's twist is a direct backside contact to the source and drain, with no detour through extra structures, which is also why it is the hardest variant to manufacture.

3. Flipping the wafer in five steps

Step 1: Build the ground floor and ceiling

Transistors and signal metal layers are built on the front of a ~0.7 mm silicon wafer as usual, minus the main power network.

Step 2: Bond a carrier wafer

Because the wafer is about to lose most of its thickness, it is bonded face-down to a second wafer that acts as a mechanical support.

Step 3: Flip it

The old bottom now faces up and becomes the new working surface.

Step 4: Thin it to far below hair width

Grinding plus CMP removes nearly all of the original few-hundred-micron substrate. A human hair is about 50–100 µm; what remains is dramatically thinner.

Step 5: Wire power from the back

Tiny contacts are opened and aligned to the transistors above, then thicker power metal is deposited and routed to the package.

4. Why it is hard

  • Alignment: hitting nanometre-scale devices from the reverse side.
  • Thinning uniformity across a 300 mm wafer.
  • Heat: transistors are now sandwiched between metal and bonding layers.
  • Cost and yield: bonding, flipping, thinning and backside steps all add risk.

Reader FAQ

Is A16 literally 1.6 nm?
No. It is a node name. The transistor base carries over from N2P nanosheets; the gain comes mostly from backside power.

Will it be in phones?
TSMC positions A16 for AI and HPC chips with dense power networks. Phones stay on N2-family nodes for now.

When does it ship?
Sources disagree. TSMC's April 2026 symposium roadmap shows 2027 volume production, while its VLSI 2026 paper and August Taiwanese reports still cite Q4 2026, likely process readiness versus product ramp.

Do Intel and Samsung have this?
Yes. Intel's is PowerVia. TSMC's direct-contact approach is considered the most complex of the three.

Open questions

  • First production customers have not been officially confirmed.
  • The thermal penalty of backside power and its mitigation are still thinly documented.

Watch next

Backside power fixes wiring inside the die; packaging connects the dies. The Engineering Core YouTube channel covers that next step:

Which of the five steps would you bet limits yield? Let us know in the comments.

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Sources: TSMC A16 technology page, VLSI Symposium 2026 T1.5, TrendForce (2026-04-23), Seoul Economic Daily (2026-08-21). Published by The Automation Core. Video: The Engineering Core YouTube channel.

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