Toshiba Halves SiC Trench Vth Drift at ICSCRM 2026: Gate-Oxide Process Reliability, Not Another IX800 Module

Bottom line: On 30 September 2026, Toshiba Electronic Devices & Storage announced a technology that suppresses long-term threshold-voltage (V_th) drift in trench-gate silicon-carbide MOSFETs, with details presented at ICSCRM 2026 in Yokohama (27 September–2 October 2026). The point is not another higher-voltage module launch. It is a gate-oxide interface process story: by tuning trench-region interface treatment (including nitridation conditions) and reducing the contribution of charge traps, Toshiba cut bipolar-gate-stress V_th drift to roughly 50% of commercially available trench-gate SiC MOSFETs while keeping low on-resistance (company comparison under stated stress — see below). The process is already applied to the 1200V trench SiC MOSFET TW007D120E (test-sample shipments from May 2026). Target narratives cover EV power conversion, renewables, and data-center supplies. Read this as gate-process / long-term reliability news — not the 27 September Toshiba IX800 3.3 kV industrial module, not yesterday’s Renesas 650V GaN DSC rack packaging piece, and not the pending Infineon × Eaton MVSST.

What happened

• Venue: ICSCRM 2026 (23rd International Conference on Silicon Carbide and Related Materials), Yokohama; through 2 October 2026.
• Problem: Trench-gate SiC often shows larger V_th drift than Si MOSFETs under sustained gate stress and under repeated positive/negative gate cycles — hurting drive margin and conduction loss over life.
• Approach: Map how gate-oxide interface treatment conditions correlate with V_th drift; optimize nitridation and related parameters to suppress trap-driven drift without giving up low R_on.
• Result (company): V_th drift cut to ~50% of commercial trench-gate SiC (example: 25°C, V_gs=+25V/−10V, 50% duty, ~400–500 kHz, 10¹¹ cycles).
• Product landing: 1200V TW007D120E; test samples since May 2026; NEDO project JPNP21029.
• Applications cited: EV converters, renewables, data-center power supplies.

How this differs from Toshiba IX800 (27 Sep): IX800 was about a 3.3 kV-class industrial / grid-side module package and current density. Today is about 1200V trench-gate SiC gate-oxide processing and V_th stability under bipolar gate stress. Same vendor, same SiC road — one story is “how you package high voltage,” the other is “how the trench gate survives millions of gate swings.” Do not merge them.

Four engineering takeaways

1. Trench gates buy conduction density — then pay a reliability bill
Standing the channel on its side lowers specific on-resistance and raises current density, which is exactly what EV and industrial SiC want. The gate oxide then lives on trench sidewalls and corners, where fields and interface states are less forgiving. When V_th walks, drive headroom and loss walk with it.

2. Bipolar gate cycling is not the same as DC bias alone
Real converters toggle the gate between positive turn-on and negative turn-off bias. Toshiba highlights literature on cycle-count-dependent V_th shifts and measures under +25V/−10V, high-frequency 50% duty, out to 10¹¹ cycles — a switching-life frame, not a static HTGB-only poster.

3. Interface treatment is a double-edged process knob
Nitridation and related oxide treatments traditionally cut R_on and shore up oxide integrity — but different recipes can amplify trap populations that later show up as bipolar-stress V_th drift. Toshiba’s claim is that clarifying the trap path lets them hold both low R_on and lower drift — not just publish one headline number.

4. “Halved” needs its test frame
The ~50% figure is Toshiba’s comparison versus “commercially available trench-gate SiC MOSFETs” under its stated stress conditions — not an independent multi-lab consensus curve. TW007D120E is still in test-sample status; full automotive/industrial qualification tables, high-temperature stress, dynamic R_on, and package-level results still need public datasheet cross-checks.

Open questions

• When do the full ICSCRM paper/slides publish, and do the stress matrices include elevated temperature and packaged parts?
• Which commercial SKUs and lots define the “commercial trench SiC” baseline — can third parties reproduce?
• When does the TW007D120E public datasheet lock V_th windows, reliability tables, and dynamic parameters?
• Does the optimized interface process trade off oxide TDDB or short-circuit withstand?
• How fast does the recipe expand to other voltage classes and module families (including AEC paths)?

Watch on The Engineering Core

• From 400V to 800V: The Silicon Carbide Revolution — primary; why high-voltage architectures lock to wide-bandgap.
• Efficiency vs. Power Factor: The Real Reason AI Data Centers Need SSTs — secondary; why data-center power stages also eat SiC.

Question for you: For trench-gate SiC to survive years in EV and data-center converters, do you expect the next bottleneck to hit gate-oxide / V_th stability first — or module packaging thermals and parasitics?

Sources: Toshiba Electronic Devices & Storage technical news (2026-09-30) — trench-gate SiC V_th drift suppression / ICSCRM 2026 / TW007D120E. The “~50%” drift reduction and stress conditions are company-published test results, not independent measurements by this channel.
Related: NEDO project JPNP21029.
Long-form: The Automation Core — https://theautomationcore.blogspot.com · Video: The Engineering Core YouTube channel