TSMC CoPoS Explained: Why Square Panels Fit ~1.8x More AI Packages (and Gen 1 May Skip Glass)

Bottom line: TSMC's CoPoS (Chip-on-Panel-on-Substrate) is first a geometry fix, not a glass revolution. It replaces the round 300 mm wafer that carries CoWoS interposers with a 310×310 mm square panel, so ever-larger AI packages stop wasting the wafer edge. Glass shows up in Gen 1 mostly as a temporary carrier.

What happened

• On the Q3 call on Oct 15, C.C. Wei said 5.5x-reticle advanced packaging is in volume with excellent yield, larger 9x and 14x formats are in development, and CoPoS is being developed to give customers a reasonable cost reduction. He also admitted back-end capacity is somewhat short (cnyes).
• TrendForce says TSMC has standardized CoPoS on a 310×310 mm panel, with 2026 as the tool and materials validation year, pilot production in 2027 and volume in 2H 2028 (TrendForce). DigiTimes puts volume no earlier than 2029 (via Investing.com).
• Economic Daily News reported in August that the first CoPoS line at Advanced Packaging Fab 7 in Chiayi is running, with roughly a year needed to stabilize process and yield (Seoul Economic Daily).

Engineering point 1: what round-to-square actually buys you

One reticle is 858 mm², so 5.5x is about 4,720 mm². I assumed a 69×69 mm square interposer, a 3 mm wafer edge exclusion and a 5 mm panel border, then brute-forced the grid offsets. Result: 9 sites on a 300 mm wafer versus 16 on a 310×310 mm panel, about 1.8x. At roughly 9x reticle (88×88 mm) it is 5 versus 9 (author estimates, not TSMC figures). The panel has only 36% more raw area; the rest is shape. The bigger the rectangle, the more a circle punishes you. A Yole example cited by CommonWealth Magazine points the same way: 7 interposers become 16, and utilization goes from about 45% to 81% (CommonWealth, Chinese).

Engineering point 2: Gen 1 may be glass-free

A veteran packaging engineer interviewed by CommonWealth argues the first CoPoS generation will likely be "zero-glass": the only glass is a reusable carrier that holds the build during processing (CommonWealth). The flow is organic RDL on a glass carrier, die attach, molding, carrier release, then singulation onto an organic substrate. A true glass-core substrate, where glass stays in the product, is a post-2030 volume story according to TrendForce.

Engineering point 3: warpage scales with the panel

Silicon expands at about 2.6 ppm/K; typical organic substrates sit around 15 to 17 ppm/K. Rough author math: cooling from a ~260°C reflow to room temperature (ΔT ≈ 235 K) with a 12 ppm/K mismatch gives about 0.26 mm of unconstrained length difference across an 88 mm package, and about 0.87 mm across a 300 mm panel. Real warpage is smaller because the layers constrain each other, but the scaling is the point: it grows with size. That explains the cautious 310 mm start, and why glass, whose CTE can be tuned close to silicon's, is the long-term bet.

Engineering point 4: through-glass vias and inspection decide yield

Keeping glass in the package means drilling through-glass vias. Today's preferred route is picosecond or femtosecond laser modification followed by wet etching. Microcracks from drilling, copper plating or thermal steps can propagate to neighboring vias, so inline inspection becomes a gating step (TrendForce). Tooling is its own hurdle: panel lines are not compatible with 300 mm tools, and a single FOPLP line can cost $100 to 200 million (Digital Today, citing Semiconductor Engineering).

Open questions

• Timing: 2H 2028 (TrendForce), 2029 (DigiTimes), possibly 2028 (Morgan Stanley). TSMC has not committed to a date.
• Reports that Nvidia is the first customer, and that TSMC is eyeing an AUO site, are unconfirmed.
• Panel size is not standardized: TSMC uses 310×310 mm while others push 515×510 mm or 600×600 mm.

Watch next

You Think TSMC's CoWoS is Just One Technology? Think Again! (S, R, & L Explained)

Beyond CoWoS: Why TSMC's SoIC is the Real Future of Chips

If you run a packaging or panel line, which do you expect to break first in CoPoS: warpage control, TGV yield, or tool readiness? Tell me in the comments.

Sources: cnyes, Oct 15 earnings call, TrendForce, Jun 17, TrendForce, Sep 21, CommonWealth, Jul 6, Seoul Economic Daily, Aug 11, DigiTimes via Investing.com, Digital Today. Figures marked as author estimates are my own calculations, not official numbers.
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